High-speed differential comparators (or slicers) play an important role in high-speed serial interface (“HSSI”) applications (e.g., for data signalling between two or more integrated circuit (“IC”) devices on a printed circuit board (“PCB”)). Clock and data recovery (“CDR”) circuitry, decision feedback equalizer (“DFE”) circuitry, and eye viewer circuitry all typically use high-speed comparators to sample/slice an input signal (e.g., a high-speed serial data signal) to determine (make a decision) as to whether the logical or data level of the input signal is binary 1 or binary 0 at each instant of time. The threshold voltage of known high-speed differential comparators is typically fixed at zero volts. However, in many applications a high-speed comparator circuit with a variable differential threshold would be desirable. For example, if the eye diagram of the input data signal is not symmetrical in the vertical direction (i.e., about a horizontal axis corresponding to a particular signal voltage level), sampling that data signal with a non-zero threshold can advantageously provide margins for a lower error rate. (The eye diagram of a data signal results from superimposing on a single unit interval of the signal multiple data bits from the signal. The unit interval (“UI”) is the time duration of any one bit in the data signal. The horizontal axis of a typical eye diagram is time, and the vertical axis is signal voltage.) Another example is an eye viewer design, which can benefit from having a variable threshold sampler to sweep the input signal to reconstruct an eye diagram. (Eye viewer circuitry can be circuitry that analyzes an input data signal over time in order to collect and assemble information about that signal suitable for providing a graphical display or other output indicative of the eye diagram of the data signal.) This disclosure addresses needs of the foregoing kinds.